what is a trap instruction? explain its use in operating systems. This is a topic that many people are looking for. amritsang.org is a channel providing useful information about learning, life, digital marketing and online courses …. it will help you have an overview and solid multi-faceted knowledge . Today, amritsang.org would like to introduce to you Operating System #14 What is an Interrupt? Types of Interrupts. Following along are instructions in the video below:
Hello and welcome to this video in todays video. We will look at interrupts. Interrupts.
Which forms a crucial part in all modern day operating systems so unlike normal or normal programs. That we write operating systems are even pace. That is whenever an event occurs only that the operating system executes to see what this means lets look at the slides.
Okay. So suppose you have a user process that is running so as weve seen before user process runs in user space and in the intel nomenclature. This is in ring.
3. Now this user process continues to execute on the processor until an event occurs so when this event occurs it would trigger the operating system to execute. So this triggering of the operating system will also result in a change in the privilege level.
So the system would no longer be executing in the user space. But rather it will be in privilege level 0. Or that is executing in the kernel space.
So the operating system would essentially execute and service. This particular event and at the end of that execution. The control is fed back to user space and the process will continue to execute.
So they use user space process. Which would execute after the os completes could be the same process that has user process 1 or some other user user process in this example. It is user process.
2. Lets look at how events are classified so various literature literature categorizes events in different ways. But what we will do is we will follow the categorization of events based on this particular book called the art of assembly language programming.
Which can be downloaded from this website. So in this book events are classified into three different types. These are hardware interrupts traps.
And exceptions so hardware interrupts or sometimes just called as interrupts are raised by external hardware devices for example. The network card. When it receives a packet could possibly raise an interrupt or other devices such as the keyboard mouse or a usb device when plugged in two days in a recent hardware interrupt.
So these hardware interrupts are in a synchronous and can occur at any time. Besides hardware interrupts. There are traps.
And exceptions traps are sometimes known as software interrupts. They are raised by user programs in order to invoke some operating system functionality for instance. If a user program wants to print something on the monitor.
It would invoke a trap. Which essentially would be a system call to the operating system and the os will then take care of writing the particular text or writing the particular data onto this onto the screen. The third type of event is known as exceptions these events are generated automatically by the processor itself as a result of an illegal instruction so there are two types of exceptions.
These are false and ibattz a very common example of a fault is a page fault so falls are essentially exceptions from which the processor could recover for instance when there is a page fault that occurs when a process is executing. It would result in the os or in the operating system executing and loading the required page from the swap space into the ram on the other hand. An exception.
Which is of the form abort would be very difficult to recover such as a 0 exception so when i divide by 0 exception occurs in a program typically the program would be terminated essentially the operating system has no way to recover from such a divide by 0. Exception. This particular slide shows the various classification of events into.
Exceptions. Traps and interrupts. Exceptions are further classified into false and abbots.
So we will now take a specific case of interrupts that is of hardware interrupts. So let us look at hardware interrupts in general processors. Today have a dedicated pin on the ic known as the interrupt pin.
So this pin is often shortened or just called by the int pin or in some processors as the int our pin. So devices such as the keyboard will be connected to the processor through the int pin. When a particular key is pressed on the keyboard.
It would result in the in an interrupt being generated to the processor now let us see how this particular interrupt takes place. And what happens in the processor. So the processor typically would be executing.
A program and would be executing.
Some instructions now when a key is pressed an interrupt is generated to the processor and that would result in a switch in the processor to what is known as the interrupt handler routine so in this particular case since it is the keyboard which has resulted in the interrupt the keyboard interrupt handler routine would be invoked the processor would then begin to execute this keyboard handler routine. Until an instruction such as the iret is obtained when the irate instruction gets executed the context is switched back to the program. Which was originally being run so in this way.
We see that interrupts could occur anytime during the programs execution. It would result in a new context being executed and at the end of that execution. The processor goes back to the original context.
So typically systems do not have just one device connected to the processor. There could be several devices for instance systems could have timers usb drives keyboards mouse network cards and so on however as we have seen previously the processor. Just has a single interrupt in so how is it possible then that several devices share.
The single interrupt pin in order to achieve this a special hardware is used in systems. So this is known as the interrupt controller the job of the interrupt controller is to ensure that the single pin of the interrupt is shared between multiple devices. So the interrupt controller would receive interrupts from each of these devices and then channelized that interrupt to the int pin of the processor.
The processor would then communicate with the interrupt controller to determine which of these devices had actually generated the interrupt and as a result the processor would then execute the corresponding interrupt handler routine for instance if the timer had resulted in the interrupt then the timer interrupt handler routine would be invoked on the other hand if a usb device had resulted in the interrupt. The usb interrupt handler routine would be invoked and so on thus the interrupt handler routine invoke is going to be very specific to the device that caused the interrupt to occur so one commonly used interrupt controller is known as a programmable interrupt controller. So it is numbered as eight two five nine and pictorially.
This is how it gets connected so the eight two five nine has two sides this is the input side and the output side the output is connected to the int thin of the cpu. There is also an int a pin. Which is an interrupt acknowledge pin on the other side.
We have eight irq lines irq stands here for interrupt requests so on the input side there are up to eight devices that can be connected to the a two final these devices are labeled device zero to device seven all these devices could independently request an interrupt from the cpu. The eight two five nine would then analyze that interrupts through the int int pin of the cpu. The cpu would acknowledge the interrupt through the int.
A pin and also determine which of these eight devices had requested the interrupt now what would happen if two devices request the interrupt at exactly the same time in such a case. A tufa nine would use some priority encoding. Algorithm to determine which of these devices should be given the privilege to request for the interrupt first another feature of the a tufa nine.
Is that it can be cascaded to support more than eight devices thus more than eight devices could pass interrupts to the cpu. So in legacy computers typically there are two eight two five nine controllers. Present one is configured as the master.
While the other is configured as the slave. The slave. A two final controller is connected to one of the input channels of the master e 2.
Final. So if any of these devices connected to the slave. 8.
To final request. An interrupt this interrupt is channelized to the master eight to five nine and the master eight two five nine would then channelize this interrupt to the cpu. So one limitation of this legacy configuration of the eight to five nines is the limited ir queues.
So each device could as weve seen can support only eight devices and therefore. If you have large number of devices in your system. Then you would require several a two five nine controllers to be present another major limitation of this configuration is that the support for multiprocessor and multi core platforms.
Is difficult essentially as we see now here. There is only one cpu that is connected to the master. A to finite programmable interrupt controller.
This particular int pin cannot be sent to an other cpu. Which may result in some problems in current systems. The a2 final programmable interrupt controller is placed by something known as epic or advanced programmable interrupt controller.
The configuration for the epics in modern systems is as shown over here. So each cpu in a multi core or multi processors system would have a local epoch as shown over here so processor. One has a local optic processor.
Two has its own epic processor. Three has its own local epoch and so on in addition to this there is something known as an i o epoch. Which is present in the system chipset now external devices such as keyboards mouse network cards and so on would request interrupts through the i o epoch.
Which is then channelized to one of the local epochs in each cpu thus interrupts can be distributed and prioritize between cpus also the local epochs as well as the i o epochs. Communicate through interrupt messages and ips that is inter processor. Interrupts.
So. The local epoch receives interrupts from the i o epoch and routes it to the corresponding local cpu. The local epoch can also receive some local interrupts such as interrupts from the thermal.
Which is present on the cpu. The an internal timer and so on so the local epoch could also send and receive ip ice. Which is inter processor.
Interrupts. Which allows interrupts between processors that it allows processors to do system wide functions. Like booting a load distribution.
And so on the i o epoch is present in the system. Chipset. Which is sometimes known as the northbridge this this particular epoch is used to route external interrupts into the local epoch.
So weve seen so far that we have multiple devices. Which are connected to an interrupt controller. Which could be either an epoch or in legacy systems based on the e8 to fine and controller when any of these devices.
Request. An interrupt the interrupt is channelized to the processor and it would salt in the corresponding interrupt handler routine to be invoked how does the processor. Know the location of the interrupt handler routine so the interrupt handler routine just like all other software codes or all other codes.
So the important question that one needs to ask here is how does the processor. Know the location of the interrupt handler routine. So the interrupt handler routine is just like any other software code is also executed from the ram.
So the question that we are posing here is how does the processor. Know the starting location or the address of the interrupt handler routine so in order to achieve this what happens is the following so each of the devices that are connected to the interrupt controller. Is also has a dedicated number known as the irq number so when a device requests an interrupt and the int pin in the processor gets asserted the processor would then obtain the irq number from the interrupt controller in this way the processor.
Now determines. Which of these devices has requested for the interrupt. We will now see how the processor uses the irq number in the memory of the system.
A table known as the interrupt descriptor table or id t. Is stored so. This id t.
Table is pointed to by a register stored in the processor. Known as the id tr. This is interrupt descriptor table register.
So each entry in this descriptor table. Contains information of where in memory. The corresponding interrupt.
Handler routine is present. So the processor would use the ir cue number to look into the inter interrupt descriptor table from this descriptor. The corresponding location of the interrupt handler.
Routine is obtained and thereafter the processor can then execute instructions from this handler routine. So what is a contents of the inter interrupt descriptor table in the x86 system since it also has segmentation so therefore the each interrupt descriptor would contain the segment selector as well as the offset. The segment selector as we have seen is of 16 bits and while the offset is of 32 bits so 0 bits 0.
To 15 are here and the bit 16 to 31 are present over here. There are other aspects in the interrupt descriptor such as the present bit and the descriptive privilege level so let us see how this interrupts descriptors are used in reality. So the processor would obtain the irq number or the interrupt vector from the programmable interrupt controller or the epoch and as we have seen this interrupt.
Vector is used to index into the idt table. And the corresponding interrupt or trap gate. Contains the segment selector as well as the offset to sets.
The segment selector is then used to index into the gd t. Or the ld t table from which the base address of the code segment is obtained the offset part is then taken and added to the base address to obtain the final address. Where the interrupt for procedure is present.
So the intel x86 systems support 56 different types of events. Some of these events are used internally for false and aborts while others can be called figured for hardware interrupts as well as for software interrupts. So this particular table gives some of these interrupts and exceptions that are supported by intel.
X86 systems especially we would like to see that interrupts with vector number zero. 231 are internal to the processor of these. The vector number 0.
To 20 are used for various false or ibattz. The interrupt vector numbers from 32 to 255 can be user defined so some of these user defined interrupts. I are configured as hardware interrupts while others are used as software interrupts so in the next video.
We will look at how interrupts are handled in the cpu as well as in the operating system thank you music applause. .
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